IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
5.1.32 T2CNT (060h), T1CNT (058h), and T0CNT (050h)
These registers are incremented by one every four internal clock cycles if the relevant timer is
enabled.
The Increment of Timer 0 and Timer 1 may also be controlled by external signals tmrin0 and
tmrin1 respectively, or prescaled by Timer 2.
Comparisons are made between the count registers and maxcount registers and action taken
dependent on achieving the maximum count.
The value of these registers is undefined at reset (see Table 54).
Table 54. Timer Count Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TC15–TC0
Bits [15–0]—TC15–TC0 Timer Count Value → This register has the value of the current
count of the related timer that is incremented every fourth processor clock in internal
clocked mode. Alternatively, the register is incremented each time the Timer 2 maxcount
is reached if using Timer 2 as a prescaler. Timer 0 and Timer 1 may be externally
clocked by tmrin0 and tmrin1 signals.
5.1.33 SPICON (044h) (Master Mode)
Serial Port Interrupt Control Register. This register controls the operation of the asynchronous
serial port interrupt source (SPI, Bit [10] in the Interrupt Request register). The value of this
register is 001Fh at reset (see Table 55).
Table 55. Serial Port Interrupt Control Registers
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Reserved MSK PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—Reserved → Set to 1.
Bit [3]—MSK Mask → This bit, when 0, enables the serial port to cause an interrupt.
When this bit is 1, the serial port is prevented from generating an interrupt.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the serial port interrupt
in relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown below.
IA211110517-02
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.innovasic.com
Customer Support:
Page 86 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
