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IA186ER 参数 Datasheet PDF下载

IA186ER图片预览
型号: IA186ER
PDF下载: 下载PDF文件 查看货源
内容描述: 16位/ 8位微控制器与内存 [16-Bit/8-Bit Microcontrollers with RAM]
分类和应用: 微控制器
文件页数/大小: 146 页 / 3147 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186ER/IA188ER  
Data Sheet  
16-Bit/8-Bit Microcontrollers with RAM  
February 25, 2013  
Bits [155]Reserved Set to 0.  
Bit [4]LTM Level-Triggered Mode The int4 interrupt may be edge- or level-  
triggered, depending on the value of the bit. If LTM is 1, int4 is active high level-  
sensitive interrupt. If 0, it is a rising-edge triggered interrupt. The interrupt int4 must  
remain active (high) until serviced.  
Bit [3]MSK Mask The int4 signal can cause an interrupt if the MSK bit is 0. The  
int4 signal cannot cause an interrupt if the MSK bit is 1.  
Bits [20]PR2PR0 Priority These bits define the priority of the interrupt in relation  
to other interrupt signals. The interrupt priority is the lowest at 7 upon reset. The values  
of PR2PR0 are shown in the above table.  
5.1.36 I3CON (03eh) and I2CON (03ch) (Master Mode)  
INT2/INT3 CONtrol Register. The int2 and int3 are designated as interrupt type 0eh and 0fh,  
respectively, and may be configured as the interrupt acknowledge pins inta0_n and inta1_n in  
cascade mode. The value of these registers is 000Fh at reset (see Table 58).  
Table 58. INT2/INT3 Control Register  
15 14 13 12 11 10  
Reserved  
9
8
7
6
5
4
3
2
1
0
LTM MSK PR2PR0  
Bits [155]Reserved Set to 0.  
Bit [4]LTM Level-Triggered Mode The int2 or int3 interrupt may be edge- or level-  
triggered depending on the value of this bit. If LTM is 1, int2 or int3 is an active high  
level-sensitive interrupt. If 0, int2 or int3 is a rising-edge-triggered interrupt. The  
interrupt int2 or int3 must remain active (high) until acknowledged.  
Bit [3]MSK Mask The int2 or int3 signal can cause an interrupt if the MSK bit is 0.  
The int2 or int3 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask  
Register has a duplicate of this bit.  
Bits [20]PR2PR0 Priority These bits define the priority of the interrupt int2 or  
int3 in relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset.  
The values of PR2PR0 are shown above.  
5.1.37 I1CON (03ah) and I0CON (038h) (Master Mode)  
INT0/INT1 CONtrol Register. The int0 and int1 are designated as interrupt type 0ch and 0dh,  
respectively, and may be configured to use the interrupt acknowledge pins inta0 and inta1 in  
cascade mode. The value of these registers is 000Fh at reset (see Table 59).  
IA211110517-02  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.innovasic.com  
Customer Support:  
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