IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 65. Interrupt Status Register (Slave Mode)
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DHLT
Reserved
TMR2–TMR0
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed.
Bits [14–3]—Reserved.
Bits [2–0]—TMR2–TMR0 Timer Interrupt Request → A pending interrupt request is
indicated by the corresponding timer, when any of these bits is 1.
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
5.1.44 REQST (02eh) (Master Mode)
Interrupt REQueST Register. This is a read-only register and such a read results in the status of
the interrupt request bits presented to the interrupt controller. The REQST register is undefined
on reset (see Table 66).
Table 66. Interrupt Request Register (Master Mode)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved SPI WD
I4–I0
D1–D0 Reserved TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Request → This is the serial port interrupt state and
when enabled is the logical OR of all the serial port 0 interrupt sources, THRE, RDR,
BRKI, FER, PER, and OER.
Bit [9]—WD Watchdog Timer Interrupt Request → When it is a 1, the watchdog
interrupt state indicates that an interrupt is pending.
Bits [8–4]—I4–I0 Interrupt Requests → When set to 1 indicates that the relevant
interrupt has a pending interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt Request → When set to 1 indicates that the
respective DMA channel has a pending interrupt.
Bit [1]—Reserved.
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