IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the
logical OR of the timer interrupt requests. When set to 1 indicates that the timer control
unit has a pending interrupt.
5.1.45 REQST (02eh) (Slave Mode)
This is a read-only register and such a read results in the status of the interrupt request bits
presented to the interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, or TMR0) occurs, the respective bit
is set to 1. The internally generated interrupt acknowledge resets these bits. The REQST
register contains 0000h on reset (see Table 67).
Table 67. Interrupt Request Register (Slave Mode)
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TMR2 TMR1 D1–D0 Reserved TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Interrupt Requests → When set to 1 indicates that Timer 2 has a pending
interrupt.
Bit [4]—TMR1 Interrupt Requests → When set to 1 indicates that Timer 1 has a pending
interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt Request → When set to 1 indicates that the
respective DMA channel has a pending interrupt.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt Request → When set to 1 indicates that Timer 0 has a
pending interrupt.
5.1.46 INSERV (02ch) (Master Mode)
IN-SERVice Register. The interrupt controller sets the bits in this register when the interrupt is
taken. Writing the corresponding interrupt type to the End-of-Interrupt (EOI) register clears each
of these bits.
When one of these bits is set, an interrupt request will not be generated by the microcontroller for
the respective source. This prevents an interrupt from interrupting itself if interrupts are enabled
in the ISR. This restriction is bypassed in Special Fully nested mode for the int0 and int1
sources. The INSERV register contains 0000h on reset (see Table 68).
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