IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 63. DMA and Interrupt Control Register (Slave Mode)
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the DMA interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.42 INTSTS (030h) (Master Mode)
INTerrupt STatuS Register. The Interrupt status register contains the interrupt request status of
each of the three timers, Timer 2, Timer 1, and Timer 0 (see Table 64).
Table 64. Interrupt Status Register (Master Mode)
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DHLT
Reserved
TMR2–TMR0
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed. Interrupt handlers and other time-critical software may modify
this bit directly to disable DMA transfers. However, the DHLT bit should not be
modified by software if the timer interrupts are enabled as the function of this register
because an interrupt request register for the timers would be compromised.
Bits [14–3]—Reserved.
Bits [2–0]—TMR2–TMR0 Timer Interrupt Request → A pending interrupt request is
indicated by the corresponding timer, when any of these bits is 1.
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
5.1.43 INTSTS (030h) (Slave Mode)
When nonmaskable interrupts occur, the interrupt status register controls DMA operation and the
interrupt request status of each of the three timers, Timer 2, Timer 1, and Timer 0 (see Table 65).
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