IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Values of PR2–PR0 by Priority
Priority
PR2–PR0
(High) 0 000b
1
2
3
4
5
6
001b
010b
011b
100b
101b
110b
(Low) 7 111b
5.1.34 WDCON (042h) (Master Mode)
WatchDog Timer Interrupt Control Register. These registers control the operation of the
Watchdog Timer interrupt source. The value of this register is 000Fh at reset (see Table 56).
Table 56. Watchdog Timer Interrupt Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Reserved MSK PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—Reserved → Set to 0.
Bit [3]—MSK Mask → This bit, when 0, enables the Watchdog Timer to cause an
interrupt. When this bit is 1 prevents the Watchdog Timer from generating an interrupt.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the Watchdog Timer
interrupt in relation to other interrupt signals. The interrupt priority is the lowest at 7 at
reset. The values of PR2–PR0 are shown in the above table.
5.1.35 I4CON (040h) (Master Mode)
This register controls the operation of the int4 signal, which is only intended for use in fully
nested mode. The interrupt is assigned to type 10h. The value of the I4CON register is 000Fh at
reset (see Table 57).
Table 57. INT4 Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
LTM MSK PR2–PR0
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