IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 59. INT0/INT1 Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
C
4
3
2
1
0
SFNM
LTM MSK PR2–PR0
Bits [15–7]—Reserved → Set to 0.
Bit [6]—SFNM Special Fully Nested Mode → This bit enables fully nested mode for int0
or int1 when set to 1.
Bit [5]—C Cascade Mode → This bit enables cascade mode for int0 or int1 when set
to 1.
Bit [4]—LTM Level-Triggered Mode → The int0 or int1 interrupt may be edge- or level-
triggered depending on the value of the bit. If LTM is 1, int0 or int1 is an active high-
level-sensitive interrupt. If 0, either is a rising-edge-triggered interrupt and must remain
active (high) until acknowledged.
Bit [3]—MSK Mask → The int0 or int1 signal can cause an interrupt if the MSK bit is 0.
If it is 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the int0 or int1 in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.38 TCUCON (032h) (Master Mode)
Timer Control Unit Interrupt CONtrol Register. The three timers have their interrupts assigned
to types 08h, 12h, and 13h and are configured by this register. The value of this register is 000Fh
at reset (see Table 60).
Table 60. Timer Control Unit Interrupt Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → An interrupt source may cause an interrupt if the MSK bit is 0. If
1, it cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the timer interrupt in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
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