IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
5.1.7 CDRAM (0e2h)
The Clock Prescaler Register determines the period between refresh cycles. The Count for
Dynamic RAM (CDRAM) register is undefined at reset (see Table 23).
Table 23. Count for Dynamic RAM Refresh Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
RC8–RC0
Bits [15–9]—Reserved → These bits read back as 0.
Bits [8–0]—RC8–RC0 → These bits hold the clock count interval between refresh
cycles. In power-save mode, the refresh counter value should be adjusted to account for
the clock divider value in PDCON.
Note: This value should not be set to less than 18 (12h), else there would
never be sufficient bus cycles available for the processor to execute code.
5.1.8 MDRAM (0e0h)
The Memory Partition Register holds the a19–a13 address bits of the 20-bit base refresh address.
The MDRAM register contains 0000h at reset (see Table 24).
Table 24. Memory Partition for Dynamic RAM Refresh Control Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
M6–M0
Reserved
Bits [15–9]—M6–M0 → Upper bits corresponding to address bits a19–a13 of the 20-bit
memory refresh address. These bits are not available on the a19–a0 bus. When using
PSRAM mode, M6–M0 must be programmed to 0000000b.
Bits [8–0]—Reserved → These bits read back as 0.
5.1.9 D1CON (0dah) and D0CON (0cah)
DMA CONtrol Registers. DMA Control Registers control operation of the two DMA channels.
The D0CON and D1CON registers are fff9h at reset (see Table 25).
Table 25. DMA Control Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM/IOn DDEC DINC SM/IOn SDEC SINC TC INT SYN1–SYN0 P TDRQ Res CHG ST Bn/W
IA211110517-02
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 64 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
