IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bit [11]—TEST → This bit is reserved for chip test and should be always set to 0.
Bits [10–8]—Reserved.
Bits [7–0]—COUNT → Control the timeout period for the WDT as follows:
Ttimeout = 2 exponent/frequency
(Equation 1)
Where:
Ttimeout
= The WDT timeout period in seconds.
frequency = The processor frequency in hertz.
exponent = Is based upon count as shown below:
Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] Exponent
0
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
1
0
X
X
X
X
X
1
0
X
X
X
X
1
0
0
0
0
X
X
X
1
0
0
0
0
0
X
X
1
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
NA
10
20
21
22
23
24
25
26
0
0
0
5.1.6 EDRAM (0e4h)
The Enable RCU Register provides control and status for the refresh counter. The EDRAM
register contains 0000h at reset (see Table 22).
Table 22. Enable Dynamic RAM Refresh Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
E
T8–T0
Bit [15]—E → When set to 1, the refresh counter is enabled and mcs3_n is configured to
act as rfsh_n. Clearing E empties the refresh counter and disables refresh requests. The
refresh address is unaffected by clearing E.
Bits [14–9]—Reserved → These bits read back as 0.
Bits [8–0]—T8–T0 → These bits hold the current value of the refresh counter. They are
read-only.
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