IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bit [9]—CAF → When set to 1, the clkouta output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [8]—CAD → When set to 1, the clkouta output is tri-stated. When 0, it is driven as
an output per the CAF bit.
Bits [7–3]—Reserved → These bits read back as 0.
Bits [2–0]—F2–F0 → These bits control the clock divider as shown below.
Note: PSEN must be 1 for the clock divider to function.
F2 F1 F0 Divider Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divide by 1 (20)
Divide by 2 (21)
Divide by 4 (22)
Divide by 8 (23)
Divide by 16 (24)
Divide by 32 (25)
Divide by 64 (26)
Divide by 128 (27)
5.1.5 WDTCON (0e6h)
The WatchDog Timer control Register provides control and status for the WDT. The WDTCON
contains c080h at reset (see Table 21).
Table 21. Watchdog Timer Control Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENA WRST RSTFLAG NMIFLAG TEST
RES
COUNT
Bit [15]—ENA → When set to 1, the WDT is enabled. When 0, it is disabled.
Bit [14]—WRST → When set to 1, an internal WDT reset is generated when the WDT
timeout count (COUNT) is reached. When 0, an NMI will be generated once WDT
timeout count is reached and the NMIFLAG bit is 0. If the NMIFLAG bit is 1, an
internal WDT reset is generated when the WDT timeout count is reached.
Bit [13]—RSTFLAG → When set to 1, a WDT timeout event has occurred. This bit may
be cleared by software or by an external reset.
Bit [12]—NMIFLAG → When set to 1, a WDT NMI event has occurred. This bit may
be cleared by software or by an external reset. If this bit is 1 when WDT timeout occurs,
an internal WDT reset is generated regardless of the state of WRST.
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