fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
p2ly
dbg
Port 2 LED Yellow. When this bit is set, the port 2 LED will be driven to the
yellow color. If this bit is reset, the port 2 LED will be driven to the green
color. Firmware can place port 2 in reset and set/reset this bit to test
yellow/green color LEDs.
Internal Port Debug Mode. When this bit is set, the internal port connected to
the host CPU will operate in promiscuous mode and will forward all traffic
received on ports 1 and 2 to host CPU. When the combined traffic received on
ports 1 and 2 exceed the bandwidth capacity of 100Mbps of the internal port,
frames will be dropped on the internal port. Hence this setting must be used
only for debug purposes and not during normal operation.
dfc
Disable Flow Control. When this bit is set, flow control is disabled on all
ports in both full and half duplex modes.
dbs
dms
ulfe
Disable Broadcast Storm Control. When this bit is set, broadcast storm
control will be disabled.
Disable Multicast Storm Control. When this bit is set multicast storm control
will be disabled.
Unicast MAC Address Learning and Filtering Enable. When this bit is set,
dynamic unicast MAC address learning and filtering is enabled. To flush
unicast MAC address learning table reset this bit and then set it again.
9.2.16 Switch IRQ Event Register
Mnemonic
type offset bits 15
14
13
0
12
0
11
0
10
pit
0
9
8
7
6
5
4
3
2
1
0
SW_Event
R/W 0x52
lst2 lst1
p2l p1l bto2 bto1 brx2 brx1 rbs2 rbs1 lirq2 lirq1
Power-up Defaults
0
0
0
0
0
0
0
0
0
0
0
0
All interrupt requests from the Switch IRQ Event register will be delivered to the host
CPU through the sw_event_irq_n signal.
lirq1
Port 1 Link Status Change IRQ. When a change of status occurs on the lst1
bit, then the lirq1 will be set. When the l1m bit in the Switch Mask register is
also set, then an interrupt is delivered to the host CPU. This bit can be reset by
writing a ‘1’ to it.
lirq2
Port 2 Link Status Change IRQ. When a change of status occurs on the lst2
bit, then the lirq2 will be set. When the l2m bit in the Switch Mask register is
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