fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
rbm2
Port 2 Ring Beacon State Change IRQ Mask. When this bit is set and the
rbs2 bit in the Switch Event register is also set, an interrupt is delivered to the
host CPU.
brm1
brm2
btm1
btm2
p1lm
p2lm
pitm
Port 1 Beacon Received IRQ Mask. When this bit is set and the brx1 bit in
the Switch Event register is also set, an interrupt is delivered to the host CPU.
Port 2 Beacon Received IRQ Mask. When this bit is set and the brx2 bit in
the Switch Event register is also set, an interrupt is delivered to the host CPU.
Port 1 Beacon Timeout IRQ Mask. When this bit is set and the bto1 bit in
the Switch Event register is also set, an interrupt is delivered to the host CPU.
Port 2 Beacon Timeout IRQ Mask. When this bit is set and the bto2 bit in
the Switch Event register is also set, an interrupt is delivered to the host CPU.
Port 1 Loop IRQ Mask. When this bit is set and the p1l bit in the Switch
Event register is also set, an interrupt is delivered to the host CPU.
Port 2 Loop IRQ Mask. When this bit is set and the p2l bit in the Switch
Event register is also set, an interrupt is delivered to the host CPU.
Periodic Interval Timer IRQ Mask. When this bit is set and the pit bit in the
Switch Event register is also set, an interrupt is delivered to the host CPU.
9.2.18 Port 1 Seed Register
Mnemonic
type offset bits 15
R/W 0x56
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Prt1Seed
p1seed
Power-up Defaults
0
0
0
p1seed Port 1 Seed. When the port 1 is in half duplex mode, this field can be used to
load a 10-bit seed value into the linear feedback shift register that is used for
the truncated binary exponential back off algorithm.
9.2.19 Port 2 Seed Register
Mnemonic
type offset bits 15
R/W 0x58
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Prt2Seed
p2seed
Power-up Defaults
0
0
0
65
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