fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
also set, then an interrupt is delivered to the host CPU. This bit can be reset by
writing a ‘1’ to it.
rbs1
rbs2
Port 1 Ring Beacon State Change IRQ. When a ring beacon is received
through port 1 and a change of State field in the frame is detected when
compared to the previous beacon, this bit is set. When the rbm1 bit in the
Switch Mask register is also set, an interrupt is delivered to the host CPU. This
bit can be reset by writing a ‘1’ to it.
Port 2 Ring Beacon State Change IRQ. When a ring beacon is received
through port 2 and a change of State field in frame is detected when compared
to the previous beacon, this bit is set. When the rbm2 bit in the Switch Mask
register is also set, an interrupt is delivered to the host CPU. This bit can be
reset by writing a ‘1’ to it.
brx1
brx2
bto1
bto2
p1l
Port 1 Beacon Received IRQ. When a ring beacon is received through port 1,
this bit is set. When the brm1 bit in the Switch Mask register is also set, an
interrupt is delivered to the host CPU. This bit can be reset by writing a ‘1’ to
it.
Port 2 Beacon Received IRQ. When a ring beacon is received through port 2,
this bit is set. When the brm2 bit in the Switch Mask register is also set, an
interrupt is delivered to the host CPU. This bit can be reset by writing a ‘1’ to
it.
Port 1 Beacon Timeout IRQ. When a ring beacon is not received through
port 1 within the beacon timeout period, this bit is set. When the btm1 bit in
the Switch Mask register is also set, an interrupt is delivered to the host CPU.
This bit can be reset by writing a ‘1’ to it.
Port 2 Beacon Timeout IRQ. When a ring beacon is not received through
port 2 within the beacon timeout period, this bit is set. When the btm2 bit in
the Switch Mask register is also set, an interrupt is delivered to the host CPU.
This bit can be reset by writing a ‘1’ to it.
Port 1 Loop IRQ. When a frame with the same source address field as the
host CPU MAC address is received on port 1, this bit is set. When the p1lm bit
in the Switch Control register is also set, an interrupt is delivered to the host
CPU. This bit indicates a network misconnection resulting in a loop when not
in ring redundancy mode. This should be flagged to the user, indicating a
network fault condition. This bit can be cleared by writing a ‘1’ to it.
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