IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
level-sensitive interrupt. If 0, it is a rising-edge triggered interrupt. The interrupt int0 or
int1 must remain active (high) until acknowledged.
Bit [3]—MSK Mask → The int0 or int1 signal can cause an interrupt if the MSK bit is 0.
The int0 or int1 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask
Register has a duplicate of this bit.
Bit [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupt
int0 or int1 in relation to other interrupt signals. The interrupt priority is the lowest at 7
at reset. The values of PR2–PR0 are shown above.
5.1.38 TCUCON (032h) (Master Mode)
Timer Control Unit Interrupt CONtrol Register. The three timers, Timer2, Timer1, and Timer0,
have their interrupts assigned to types 08h, 12h, and 13h and are configured by this register. The
value of these registers is 000Fh at reset (see Table 59).
Table 59. Timer Control Unit Interrupt Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2 PR1 PR0
Bits [15–4]—Reserved. Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt
Mask Register has a duplicate of this bit.
Bit [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupts
in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset.
The values of PR2–PR0 are shown above.
5.1.39 T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h) (Slave Mode)
Timer INTerrupt CONtrol Register. The three timers, Timer2, Timer1, and Timer0, each have
an interrupt control register, whereas in master mode all three are masked and prioritized in one
register (TCUCON). The value of these registers is 000Fh at reset (see Table 60).
Table 60. Timer Interrupt Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
MSK PR2–PR0
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