IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Values of PR2–PR0 by Priority
Priority PR2–PR0
(High) 0 000b
1
2
3
4
5
6
001b
010b
011b
100b
101b
110b
(Low) 7 111b
5.1.35 I4CON (040h) (Master Mode)
INT4 CONtrol Register. The int4 signal is intended only for use in fully nested mode and is not
available in cascade mode. The value of the I4CON register is 000Fh at reset (see Table 56).
Table 56. INT4 Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
LTM MSK PR2 PR1 PR0
Bits [15–5]—Reserved. Set to 0.
Bit [4]—LTM Level-Triggered Mode → The int4 interrupt may be edge- or level-
triggered, depending on the value of the bit. If LTM is 1, int4 is active high level-
sensitive interrupt. If 0, it is a rising-edge triggered interrupt. The interrupt int4 must
remain active (high) until serviced.
Bit [3]—MSK Mask → The int4 signal can cause an interrupt if the MSK bit is 0. The
int4 signal cannot cause an interrupt if the MSK bit is 1.
Bit [2–0]—PR [2–0] Priority → These bits define the priority of the serial port interrupt
in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset.
The values of PR2–PR0 are shown above.
5.1.36 I3CON (03eh) and I2CON (03ch) (Master Mode)
INT2/INT3 CONtrol Register. INT2 and INT3 are designated as interrupt type 0eh and 0fh,
respectively.
The int2 and int3 pins may be configured as the interrupt acknowledge pins inta0 and inta1,
respectively, the signals in cascade mode. The value of these registers is 000Fh at reset (see
Table 57).
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