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AM186ES-33VIW 参数 Datasheet PDF下载

AM186ES-33VIW图片预览
型号: AM186ES-33VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 154 页 / 1714 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186ES/IA188ES  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
November 15, 2011  
Bit [15]DHLT DMA Halt DMA activity is halted when this bit is 1. It is set to 1  
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET  
instruction is executed. Interrupt handlers and other time critical software may modify  
this bit directly to disable DMA transfers. However, the DHLT bit should not be  
modified by software if the timer interrupts are enabled as the function of this register as  
an interrupt request register for the timers would be compromised.  
Bits [143]Reserved.  
Bit [20]TMR [20] Timer Interrupt Request A pending interrupt request is  
indicated by the respective timer, when any of these bits is 1.  
Note: The TMR bit in the REQST register is a logical OR of these timer  
interrupt requests.  
5.1.44 REQST (02eh) (Master Mode)  
Interrupt REQueST Register. This is a read-only register and such a read results in the status of  
the interrupt request bits presented to the interrupt controller. The REQST register is undefined  
on reset (see Table 65).  
Table 65. Interrupt Request Register (Master Mode)  
15 14 13 12 11  
Reserved  
10  
9
8
7
6
5
4
3
2
1
0
SP0 SP1 I4 I3 I2 I1 IO D1/I6 D0/I5 Res TMR  
Bits [1511]Reserved.  
Bit [10]SP0 Serial Port 0 Interrupt Request This is the serial port 0 interrupt state  
and when enabled is the logical OR of all the serial port 0 interrupt sources, THRE, RDR,  
BRK1, BRK0, FER, PER, and OER.  
Bit [9]SP1 Serial Port 1 Interrupt Request This is the serial port 1 interrupt state and  
when enabled is the logical OR of all the serial port 1 interrupt sources, THRE, RDR,  
BRK1, BRK0, FER, PER, and OER.  
Bits [84]I [40] Interrupt Requests When any of these bits is set to 1, it indicates  
that the relevant interrupt has a pending interrupt.  
Bit [3]D1/I6 DMA Channel 1/Interrupt 6 Request When set to 1, it indicates that  
either the DMA channel 1 or int6 has a pending interrupt.  
Bit [2]D0/I5 DMA Channel 0/Interrupt 5 Request When set to 1, it indicates that  
either the DMA channel 0 or int5 has a pending interrupt.  
®
IA211050902-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.innovasic.com  
Customer Support:  
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1-888-824-4184  
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