IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 70. Interrupt MASK Register (Master Mode)
15 14 13 12 11
Reserved
10
9
8
7
6
5
4
3
2
1
0
SP0 SP1 I4 I3 I2 I1 IO D1/I6 D0/I5 Res TMR
Bits [15–11]—Reserved.
Bit [10]—SP0 Serial Port 0 Interrupt Mask → Setting this bit to 1 is an indication that the
serial port 0 interrupt is masked.
Bit [9]—SP1 Serial Port 1 Interrupt Mask → Setting this bit to 1 is an indication that the
serial port 0 interrupt is masked.
Bits [8–4]—I [4–0] Interrupt Mask → When any of these bits is set to 1, it is an
indication that the relevant interrupt is masked.
Bit [3]—D1/I6 DMA Channel 1/Interrupt 6 Mask → Setting this bit to 1, is an indication
that either the DMA channel 1 or int6 interrupt is masked.
Bit [2]—D0/I5 DMA Channel 0/Interrupt 5 Mask → When set to 1, it indicates that either
the DMA channel 0 or int5 interrupt is masked.
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Mask → When set to 1, it indicates that the timer control
unit interrupt is masked.
5.1.50 IMASK (028h) (Slave Mode)
The interrupt mask register is read/write. Setting a bit in this register has the effect of setting the
MSK bit in the corresponding interrupt control register. Setting a bit to 1, masks the interrupt
request. The interrupt request is enabled when the corresponding bit is set to 0. The IMASK
register contains 003dh on reset (see Table 71).
Table 71. Interrupt MASK Register (Slave Mode)
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TMR2 TMR1 D1/I6 D0/I5 Res TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Timer2 Interrupt Mask → This bit provides the state of the mask bit in
the Timer Interrupt Control register. When set to 1, it indicates that the interrupt request
is masked.
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