XMC4500
XMC4000 Family
Electrical Parameters
Demultiplexed Write Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Data Hold
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Duration Limits in
EBU_CLK Cycles
1...15
1...31
0...15
0...15
0...15
1...15
A[max:0]1)
Next
Valid Address
pv +
Addr.
t30
pv +
t31
pv +
ta
CS[3:0]
pv +
t32
CSCOMB
pv +
t33
pv +
ta
ADV
RD
pv +
t39
pv +
ta
RD/WR
t34
pv +
ta
pv +
ta
BC[3:0]
WAIT
t36
t35
t37
pv +
t38
D[15:0]2)
Data Out
1) Address A[max:16] on pins A[max:16], Address A[15:0] on pins AD[31:16]
2) Data D[15:0] on pins AD[15:0]
pv = programmed value,
EBU_DeMuxWR_Async.vsd
T
EBU_CLK * sum (corresponding bitfield values)
Figure 31
Demultiplexed Write Access
Data Sheet
94
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
