XMC4500
XMC4000 Family
Electrical Parameters
Multiplexed Read Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.) Delay Phase
Command
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Duration Limits in
EBU_CLK Cycles
1...15
0...7
1...31
0...15
0...15
1...15
A[max:16]1)
Next
Valid Address
Addr.
pv +
pv +
t0
t1
t2
pv +
ta
CS[3:0]
CSCOMB
pv +
t3
pv +
ta
ADV
RD
pv +
ta
pv +
pv +
t9
ta
RD/WR
pv +
ta
t4
BC[3:0]
WAIT
pv +
t5
t6
pv +
t14
t7
t8
pv +
t13
AD[31:0]2)
Address Out
Data In
1) For 16-bit MUX and Twin 16-bit MUX only
2)* 16-bit MUX:
- Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX:
- Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values)
EBU_MuxRD_Async.vsd
Figure 28
Multiplexed Read Access
Data Sheet
90
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
