XMC4500
XMC4000 Family
Electrical Parameters
Demultiplexed Read Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Duration Limits in
EBU_CLK Cycles
1...15
1...31
0...15
0...15
1...15
A[max:0]1)
Next
Valid Address
Addr.
pv +
pv +
pv +
t0
ta
t1
t2
CS[3:0]
CSCOMB
pv +
t3
pv +
ta
ADV
RD
pv +
ta
pv +
t9
RD/WR
pv +
ta
pv +
ta
t4
BC[3:0]
WAIT
pv +
t5
t6
t7
t8
D[15:0]2)
Data In
1) Address A[max:16] on pins A[max:16], Address A[15:0] on pins AD[31:16]
2) Data D[15:0] on pins AD[15:0]
pv = programmed value,
EBU_DeMuxRD_Async.vsd
TEBU_CLK * sum (corresponding bitfield values)
Figure 29
Demultiplexed Read Access
Data Sheet
91
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
