XMC4500
XMC4000 Family
Electrical Parameters
3.3.10.4 EBU SDRAM Access Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
Table 55
EBU SDRAM Access SDCLKO Signal Timing Parameters
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
Typ. Max.
dition
SDCLKO period
t1
t2
t3
t4
t5
CC 12.5
SR 5.5
SR 3.75
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
SDCLKO high time
SDCLKO low time
SDCLKO rise time
SDCLKO fall time
–
–
SR
SR
–
–
3.0
3.0
t1
0.9 VDDP
0.1 VDDP
SDCLKO
0.5 VDDP
t2
t3
t5
t4
EBU_SDCLKO.vsd
Figure 34
EBU SDRAM Access CLKOUT Timing
Data Sheet
98
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
