XMC4500
XMC4000 Family
Electrical Parameters
Multiplexed Write Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Data Hold
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Duration Limits in
EBU_CLK Cycles
1...15
1...31
0...15
0...15
0...15
1...15
A[max:16]1)
Next
Valid Address
pv +
Addr.
t30
pv +
t31
pv +
ta
CS[3:0]
pv +
t32
CSCOMB
pv +
t33
pv +
ta
ADV
RD
pv +
ta
pv +
pv +
t39
RD/WR
t34
ta
pv +
ta
BC[3:0]
WAIT
t36
t35
pv +
t14
t37
pv +
pv +
t38
t13
AD[31:0]2)
Data Out
Address Out
1) For 16-bit MUX and Twin 16-bit MUX only
2)* 16-bit MUX:
- Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX:
- Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values)
EBU_MuxWR_Async.vsd
Figure 30
Multiplexed Write Access
Data Sheet
93
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
