XMC4500
XMC4000 Family
Electrical Parameters
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(12)
tCLK_DELAY + tOH + tDATA_DELAY + tTAP_DELAY > tIH_H
tCLK_DELAY + tDATA_DELAY > tIH_H – tOH – tTAP_DELAY
tCLK_DELAY + tDATA_DELAY > 2 – 2,5 – tTAP_DELAY
tCLK_DELAY + tDATA_DELAY > – 0,5 – tTAP_DELAY
The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always
fulfilled.
Data Sheet
87
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
