XMC4500
XMC4000 Family
Electrical Parameters
No clock delay:
(7)
tODLY_H + tDATA_DELAY + tTAP_DELAY + tISU < tWL
With clock delay:
(8)
tODLY_H + tDATA_DELAY + tTAP_DELAY + tISU < tWL + tCLK_DELAY
(9)
tDATA_DELAY + tTAP_DELAY – tCLK_DELAY < tWL – tISU – tODLY_H
tDATA_DELAY – tCLK_DELAY < tWL – tISU – tODLY_H – tTAP_DELAY
tDATA_DELAY – tCLK_DELAY < 10 – 6 – 14 – tTAP_DELAY
tDATA_DELAY – tCLK_DELAY < – 10 – tTAP_DELAY
The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL
=
10 ns.
High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(10)
tCLK_DELAY < tWL + tOH_H + tDATA_DELAY + tTAP_DELAY – tIH
tCLK_DELAY – tDATA_DELAY < tWL + tOH_H + tTAP_DELAY – tIH
tCLK_DELAY – tDATA_DELAY < 10 + 2 + tTAP_DELAY – 2
tCLK_DELAY – tDATA_DELAY < 10 + tTAP_DELAY
The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of
t
WL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
Data Sheet
85
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
