XMC4500
XMC4000 Family
Electrical Parameters
With clock delay:
(2)
tODLY_F + tDATA_DELAY + tTAP_DELAY + tISU < tWL + tCLK_DELAY
(3)
tDATA_DELAY + tTAP_DELAY + tWL < tPP + tCLK_DELAY – tISU – tODLY_F
tDATA_DELAY + tTAP_DELAY + 20 < 40 + tCLK_DELAY – 5 – 10
tDATA_DELAY < 5 + tCLK_DELAY – tTAP_DELAY
The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns.
Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(4)
tCLK_DELAY < tWL + tOH_F + tDATA_DELAY + tTAP_DELAY – tIH
tCLK_DELAY < 20 + tDATA_DELAY + tTAP_DELAY – 5
tDATA_DELAY < 15 + tCLK_DELAY + tTAP_DELAY
The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of
t
WL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
Data Sheet
81
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
