XMC4500
XMC4000 Family
Electrical Parameters
Table 47
SD Card Bus Timing for Full-Speed Mode1) (cont’d)
Parameter
Symbol
Values
Unit Note/ Test
Condition
Min.
Max.
14
SD card output valid time
SD card output hold time
tODLY
tOH
−
ns
ns
0
−
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Full-Speed Output Path (Write)
tpp (Clock Cycle)
SD Clock at
Host Pin
Driving
Edge
tCLK_DELAY
SD Clock at
Card Pin
Sampling
Edge
Output Valid Time: tODLY_H
Output Hold Time: tOH_H
tWL
Output at
Host Pins
Output at
Card Pins
tDATA _DELAY
+ tTAP_DELAY
tIH
tISU
Figure 24
Full-Speed Output Path
Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
No clock delay:
(1)
tODLY_F + tDATA_DELAY + tTAP_DELAY + tISU < tWL
Data Sheet
80
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
