XMC4500
XMC4000 Family
Electrical Parameters
Table 43
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Min.
Values
Typ.
-
Unit Note /
Test Condition
Max.
Fall time of both SDA and t1
SCL CC/SR 0.1*Cb
20 +
300
ns
ns
2)
Rise time of both SDA and t2
20 +
-
300
SCL
CC/SR 0.1*Cb
2)
Data hold time
Data set-up time
t3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µs
ns
µs
µs
µs
µs
µs
µs
CC/SR
t4
100
1.3
0.6
0.6
0.6
0.6
1.3
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
76
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
