OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
14.2
Failure signalization in the SPI data output
When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong
SPI commands can be either an invalid control command requesting to go to an SBC mode which is not
allowed by the state machine, for example from SBC Stop mode to SBC Sleep mode. In this case the diagnosis
bit ‘SPI_FAIL’ is set. This bit can be only reset by actively clearing it using an SPI command.
Invalid SPI commands are listed below:
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•
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Illegal state transitions:
Going from SBC Stop to SBC Sleep mode. In this case, the SBC enters in addition the SBC Restart mode.
Trying to go to SBC Stop or SBC Sleep mode from SBC Init mode. In this case, the SBC enters
SBC Normal mode
Attempting to change the watchdog settings during Stop mode ;.
Only WD trigger, returning to SBC Normal mode, select Software Reset, set to SBC Stop mode to return
from PWM to PFM when automatic buck mode transition has happened and read and clear commands are
valid SPI commands in SBC Stop mode
Attempt to go to Sleep mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers are cleared. In
this case, the SPI_FAIL bit is set and the SBC enters Restart mode.
Note that at least one wake source must be activated in order to avoid a deadlock situation in Sleep mode,
i.e. the SBC would not be able to wake up anymore. There is no signalling or failure handling for the
attempt to go to SBC Stop mode when all bits in the registers BUS_CTRL_1 and WK_CTRL_2 are cleared
because the microcontroller can leave this mode via SPI
Signalization of the ERR flag in the SPI data output (see Figure 46):
In addition, the number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is
discarded in case of a mismatch (0 clock cycle to enable ERR signalization). Both errors - 0 bit and 16 bit CLK
mismatch or CLK high during CSN edges - are flagged in the following SPI output by a HIGH at the data output
(SDO pin, bit ERR) before the first rising edge of the clock is received. The error logic also recognizes if CLK was
HIGH during CSN edges. The complete SPI command is ignored in these cases.
Note: It is also possible (no ERR flag is set) to quickly check for the ERR flag without sending any data bits. i.e. no
SPI clocks are sent in this case.
Datasheet
97
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
