OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
7
6...0
Register Short Name
Address
A6…A0
Read-Only (1)
C O N T R O L R E G I S T E R S
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001100
0011110
M_S_CTRL
HW_CTRL
WD_CTRL
BUS_CTRL_1
BUS_CTRL_2
WK_CTRL_1
WK_CTRL_2
WK_PUPD_CTRL
TIMER1_CTRL
SYS_STATUS_CTRL
S T A T U S R E G I S T E R S
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001100
1111110
SUP_STAT
THERM_STAT
DEV_STAT
BUS_STAT_1
BUS_STAT_2
WK_STAT_1
WK_STAT_2
WK_LVL_STAT
SMPS_STAT
FAM_PROD_STAT
read/clear
read
Figure 48 SPI bit mapping
15
14
13
12
11
10
9
8
7
6...0
Register Short Name
Data Bit 15…8
D4
Address
A6…A0
Read-Only (1)
D7
D6
D5
D3
D2
D1
D0
C O N T R O L R E G I S T E R S
M_S_CTRL
HW_CTRL
WD_CTRL
BUS_CTRL_1
BUS_CTRL_2
WK_CTRL_1
MODE_1
FSI_FO2
CHECKSUM
LIN_FLASH
LIN4_1
reserved
reserved
reserved
reserved
MODE_0
PWM_TLAG
WD_STM_EN_0
LIN_LSM
LIN4_0
TIMER1_WK_EN
reserved
reserved
reserved
SYS_STAT_6
reserved
FO_ON
WD_WIN
LIN_TXD_TO
BOOST_VH
reserved
reserved
reserved
reserved
SYS_STAT_5
VCC2_ON_1
PWM_BY_WK
WD_EN_WK_BUS
LIN1_1
LIN3_1
reserved
reserved
reserved
reserved
SYS_STAT_4
VCC2_ON_0
PWM_AUTO
MAX_3_RST
LIN1_0
LIN3_0
reserved
reserved
reserved
reserved
SYS_STAT_3
VCC1_OV_RST
BOOST_V
WD_TIMER_2
reserved
reserved
WD_STM_EN_1
reserved
VCC1_RT_1
BOOST_EN
WD_TIMER_1
CAN_1
LIN2_1
reserved
VCC1_RT_0
CFG2
WD_TIMER_0
CAN_0
LIN2_0
reserved
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001100
0011110
WK_CTRL_2
reserved
WK_PUPD_1
WK_EN
WK_PUPD_0
WK_PUPD_CTRL
TIMER1_CTRL
SYS_STATUS_CTRL
reserved
TIMER1_PER_2 TIMER1_PER_1 TIMER1_PER_0
SYS_STAT_2
SYS_STAT_7
SYS_STAT_1
SYS_STAT_0
S T A T U S R E G I S T E R S
SUP_STAT
THERM_STAT
DEV_STAT
BUS_STAT_1
BUS_STAT_2
WK_STAT_1
WK_STAT_2
WK_LVL_STAT
SMPS_STAT
POR
reserved
DEV_STAT_1
reserved
reserved
PFM_PWM
reserved
TEST
VLIN_UV
reserved
DEV_STAT_0
LIN1_FAIL_1
LIN4_FAIL_1
reserved
reserved
reserved
BST_SH
FAM_2
VCC1_OV
reserved
RO_CL_HIGH
LIN1_FAIL_0
LIN4_FAIL_0
CAN_WU
reserved
CFG2_STATE
BST_OP
VCC2_OT
reserved
FSI_FAIL
reserved
LIN3_FAIL_1
TIMER_WU
reserved
reserved
BST_GSH
FAM_0
VCC2_UV
reserved
WD_FAIL_1
reserved
LIN3_FAIL_0
reserved
LIN4_WU
reserved
VCC1_SC
TSD2
WD_FAIL_0
CAN_FAIL_1
LIN2_FAIL_1
reserved
LIN3_WU
reserved
BCK_SH
reserved
TSD1
SPI_FAIL
CAN_FAIL_0
LIN2_FAIL_0
reserved
LIN2_WU
reserved
BCK_OP
PROD_1
VCC1_UV
TPW
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001100
1111110
FO_ON_STATE
VCAN_UV
reserved
WK_WU
LIN1_WU
WK
BST_ACT
FAM_3
reserved
PROD_3
BCK_OOR
PROD_0
read/clear
read
FAM_PROD_STAT
FAM_1
PROD_2
Figure 49 Detailed SPI bit mapping
Datasheet
100
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
