OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
14.7
Electrical characteristics
Table 23 Electrical characteristics: power stage
Tj = -40°C to +150°C, VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI frequency
1)
Maximum SPI frequency
fSPI,max
–
–
4.0
MHz
P_14.8.1
SPI interface; logic inputs SDI, CLK and CSN
H-input voltage threshold
VIH
–
–
–
0.7 ×
VCC1
V
V
V
–
P_14.8.2
P_14.8.3
P_14.8.4
L-input voltage threshold
VIL
0.3 ×
VCC1
–
–
1)
Hysteresis of input voltage VIHY
Pull-up resistance at pin CSN RICSN
–
0.2 ×
VCC1
–
20
20
40
40
80
80
kΩ
kΩ
VCSN = 0.7 × VCC1 P_14.8.5
Pull-down resistance at pin RICLK/SDI
VSDI/CLK
=
P_14.8.6
SDI and CLK
0.2 × VCC1
1)
Input capacitance at pin
CSN, SDI or CLK
CI
–
10
–
–
pF
V
P_14.8.7
Logic output SDO
H-output voltage level
VSDOH
VCC1
0.4
-
VCC1
0.2
-
IDOH = -1.6 mA
IDOL = 1.6 mA
P_14.8.8
L-output voltage level
VSDOL
ISDOLK
–
0.2
–
0.4
10
V
P_14.8.9
Tri-state leakage current
-10
µA
VCSN = VCC1
;
P_14.8.10
0 V < VDO < VCC1
1)
Tri-state input capacitance CSDO
–
10
15
pF
P_14.8.11
Data input timing1)
Clock period
tpCLK
tCLKH
tCLKL
250
125
125
125
250
250
125
100
50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
P_14.8.12
P_14.8.13
P_14.8.14
P_14.8.15
P_14.8.16
P_14.8.17
P_14.8.18
P_14.8.19
P_14.8.20
Clock HIGH time
Clock LOW time
Clock LOW before CSN LOW tbef
CSN setup time
CLK setup time
tlead
tlag
Clock LOW after CSN HIGH tbeh
SDI setup time
SDI hold time
tDISU
tDIHO
Datasheet
117
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
