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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
Electrical SpecificationEBU Timings  
Table 3-70 Common Asynchronous Timings valid for 3.3V (cont’d)  
Parameter Symbol Values  
Typ.  
Unit  
Note / Test Condition  
Min.  
Max.  
Address valid to CS falling edge t15 CC  
(deviation from programmed  
value)  
-2  
-
-
-
2.5  
ns  
CL=35pF  
Address valid to ADV falling  
edge (deviation from  
t
16 CC  
-2  
-2  
2.5  
2.5  
ns  
ns  
CL=35pF  
CL=35pF  
programmed value)  
ADV falling edge -> CS falling  
edge (deviation from  
t
17 CC  
programmed value)  
Pulse wdih deviation from the  
ideal programmed width due to  
B pad asymmetry, rise delay -  
fall delay  
ta CC  
-0.8  
-0.8  
-
-
0.8  
0.8  
ns  
ns  
edge=medium;  
CL=35pF  
edge=sharp; CL=35pF  
Table 3-71 Asynchronous Read Timings valid for 3.3V  
Parameter Symbol  
Values  
Unit  
Note / Test Condition  
Min.  
Typ.  
Max.  
A(23:0) output delay to RD rising t0 CC  
edge, deviation from the ideal  
programmed value  
-2.5  
-
2.5  
ns  
CL=35pF  
Data input Hold from CS rising  
edge  
t
18 CC  
-6  
-
-
-
-
ns  
ns  
ns  
CL=35pF  
CL=35pF  
CL=35pF  
Data input Setup to CS rising  
edge  
t
19 CC  
19  
-
A(23:0) output delay to RD rising t1 CC  
edge, deviation from the ideal  
programmed value  
-2.5  
2.5  
CS rising edge to RD rising  
edge, deviation from the ideal  
programmed value  
t2 CC  
t3 CC  
t4 CC  
t5 SR  
t6 SR  
-2  
-
-
-
-
-
2.5  
4.5  
2.5  
-
ns  
ns  
ns  
ns  
ns  
CL=35pF  
CL=35pF  
CL=35pF  
CL=35pF  
CL=35pF  
ADV rising edge to RD rising  
edge, deviation from the ideal  
programmed value  
-2  
BC rising edge to RD rising  
edge, deviation from the ideal  
programmed value  
-2.5  
19  
-4  
WAIT input setup to RD rising  
edge, deviation from the ideal  
programmed value  
WAIT input hold to RD rising  
edge, deviation from the ideal  
programmed value  
-
Data Sheet  
504  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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