TC1767
Electrical Parameters
t50
SCLK1)2)
MTSR1)
t51
t51
t52
t53
Data
valid
MRST1)
SLSOx2)
t51
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 34
SSC Master Mode Timing
t54
First latching
SCLK edge
Last latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
t61
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_TmgSM
Figure 35
SSC Slave Mode Timing
Data Sheet
117
V1.3, 2009-09
INFINEON [ Infineon ]
