TC1767
Electrical Parameters
5.3.8
Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design / characterization.
5.3.8.1 Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 32
MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Data Sheet
113
V1.3, 2009-09