SAE 81C90/91
07Feb95@09:05h Intermediate Version
Mode/Status-Register
MOD
7
6
RS
r
5
TC
r
4
TWL
r
3
RWL
r
2
BS
r
1
0
Address: 10
ADE
RES
rw
IM
rw
H
Reset Value: 00
rw
H
Bit(field)
IM
Function
Init Mode
’0’: Normal mode.
’1’: Initialization mode:
write access to the configuration registers BL1, BL2, OC, BRP is enabled.
If the bit stays set, the chip enters the normal mode, with enabled access to
the configuration registers.
If this bit is set in conjunction with bit RES a hard software reset is
activated.
RES
Reset Request
’0’: Normal mode.
’1’: The chip enters the reset state:
– if bit IM = ’0’ a soft software reset takes place.
– if bit IM = ’1’ a hard software reset takes place. Further details see below.
BS
Bus State (read only)
’0’: Normal mode.
’1’: Bus Off state, the IC does not participate in bus activities.
RWL
TWL
TC
Receiver Warning Level (read only)
’0’: Receive-error counter below 96.
’1’: Receive-error counter equal or above 96.
Transmit Warning Level (read only)
’0’: Transmit-error counter below 96.
’1’: Transmit-error counter equal or above 96.
Transmission Complete (read only)
’0’: The last transmission request is not yet executed successfully.
’1’: The last transmission request was executed successfully.
RS
Receive State (read only)
’0’: No reception active.
’1’: Currently the SAE 81C90/91 is in receive mode.
ADE
Auto Decrement Enable
’0’: No automatic address decrement.
’1’: With every read or write access using the serial synchronous interface SI
the address is automatically decremented by one. So data can be
accessed sequentially without the need of writing a new address.
Semiconductor Group
19
INFINEON [ Infineon ]
