SAE 81C90/91
07Feb95@09:05h Intermediate Version
Interrupt-Mask Register
These mask bits determine if an event activates the INT pin. They do not influence the INT register.
IMSK
7
6
5
4
3
2
1
0
Address: 0A
ETCI
rw
EEPI
rw
EBOI EWUPI
rw rw
ERFI
rw
EWLI
rw
ETI
rw
ERI
rw
H
Reset Value: 00
H
Bit(field)
ERI
Function
Enable Receive Interrupt
’0’: No receive interrupt enabled.
’1’: Receive interrupts are enabled.
ETI
Enable Transmit Interrupt
’0’: No transmit interrupt enabled.
’1’: Completed transmit jobs generate interrupts.
EWLI
ERFI
EWUPI
EBOI
EEPI
ETCI
Enable Warning Level Interrupt
’0’: No warning level interrupt enabled.
’1’: There is an interrupt when the warning level is reached.
Enable Remote Frame Interrupt
’0’: No remote frame interrupt enabled.
’1’: A receive interrupt is generated after receiving a remote frame
Enable Wake Up Interrupt
’0’: No wake up interrupt enabled.
’1’: Wake-up interrupt is enabled.
Enable Bus Off Interrupt
’0’: No bus off interrupt enabled.
’1’: Bus off interrupt is enabled.
Enable Error Passive Interrupt
’0’: No error passive interrupt enabled.
’1’: Error passive interrupt is enabled.
Enable Transmit Check Error Interrupt
’0’: No transmit check interrupt enabled.
’1’: Transmit-check error interrupt is enabled.
Semiconductor Group
22
INFINEON [ Infineon ]
