SAE 81C90/91
07Feb95@09:05h Intermediate Version
Interrupt Register
INT
7
6
5
4
3
2
1
0
Address: 11
TCI
rw
EPI
rw
BOI
rw
WUPI
rw
RFI
rw
WLI
rw
TI
rw
RI
rw
H
Reset Value: 00
H
Bit(field)
RI
Function
Receive Interrupt
After a valid message has been received and filed, this bit is set and an interrupt
generated.
This bit will remain set until all bits of the registers RRR1 and RRR2 are reset.
TI
Transmit Interrupt
This bit is set and an interrupt generated as soon as a transmit request has been
processed.
WLI
Warning Level Interrupt
If at least one of the two error counters is greater than or equals 96, this bit is set
and an interrupt generated.
RFI
Remote Frame Interrupt
This interrupt is generated after reception of a remote frame.
WUPI
BOI
EPI
Wake Up Interrupt
After a wake-up this bit is set and an interrupt generated.
Bus Off Interrupt
This bit is set and an interrupt generated when the Bus Off status is entered.
Error Passive Interrupt
If at least one of the two error counters is greater than or equals 128, this bit is
set and an interrupt generated.
TCI
Transmit Check Interrupt
If the transmit-check error counter reaches 4, this bit is set and an interrupt
generated.
Note: All bits of this register must be reset by software. This is done by writing ’0’ to the respective
bit location, writing ’1’ has no effect.
An interrupt is only generated if the respective IMSK bit is set. The bits in this register are set
independent of register IMSK (see below).
The interrupt output is active for at least one bit time. The interrupt output is deactivated when
all enabled request bits are cleared. A request bit is enabled by setting its corresponding
mask bit. Masked request bits do not activate the interrupt output.
Semiconductor Group
21
INFINEON [ Infineon ]
