SAE 81C90/91
07Feb95@09:05h Intermediate Version
Control Register Summary
Register Name Address Function
Reset Read
Value Write
1)
OC
02
14
12
10
11
Output-control register
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
r/w, I
wo
r/w
r/w
r/w
r/w
r/w, I
r/w, I
wo, I
r/w
r/w
r/w
r/w
r/w
r/w
wo
wo
ro
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
CC
Clock-control register
CTRL
MOD
Control register
Mode/status register
INT
Interrupt register
IMSK
BL1
0A
00
Interrupt-mask register
H
Bit-length register 1
H
H
H
H
H
H
H
H
H
H
H
BL2
01
03
04
05
06
07
08
09
18
19
Bit-length register 2
BRP
Baud-rate prescaler
RRR1
RRR2
RIMR1
RIMR2
TRSR1
TRSR2
TRRR1
TRRR2
RRPR1
RRPR2
TSCH
TSCL
TCEC
TCD
Receive-ready register 1
Receive-ready register 2
Receive-interrupt-mask register 1
Receive-interrupt-mask register 2
Transmit-request-set register 1
Transmit-request-set register 2
Transmit-request-reset register 1
Transmit-request-reset register 2
Remote-request-pending register 1
Remote-request-pending register 2
Time-Stamp counter high byte
Time-Stamp counter low byte
Transmit-check error counter
Transmit-check data register
Port 0 port-direction register
Port 1 port-direction register
Port 0 latch register
1A
1B
H
ro
H
1C
1D
15
r/w
r/w
r/w
ro
H
H
H
H
H
16
28
XX
00
P0PDR
P1PDR
P0LR
P1LR
P0PR
P1PR
r/w
r/w
r/w
r/w
ro
H
2C
2A
00
00
00
H
H
H
H
H
H
2E
29
Port 1 latch register
Port 0 pin register
XX
XX
H
H
H
2D
Port 1 pin register
ro
H
1)
Note: ro: read only, r/w: read and write access, wo: write only, I: access only with bit IM set.
Semiconductor Group
15
INFINEON [ Infineon ]
