S29GL01GP
S29GL512P
S29GL256P
S29GL128P
Notes
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2.
t
for data polling is 45 ns when V = 1.65 to 2.7 V and is 35 ns when V = 2.7 to 3.6 V
OE IO IO
3. CE# does not need to go high between status bit reads
Figure 11.13 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ2 and DQ6
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note
A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read
cycle CE# does not need to go high between status bit reads
Figure 11.14 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE# or CE# to toggle DQ2 and DQ6.
Document Number: 002-00886 Rev. *B
Page 59 of 83
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