EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller
Dual-port
Pin list
3
Pin list
Table 2
CCG7D pinout table
GPIO port
Pin#
Pin name
Description
assignment
Negative power rail of port 0 buck high side gate driver. This is also connected to one
input terminal of zero current detection of buck low side gate driver.
1
SW1_0
Connect to the switch node (inductor) on the buck (input) side. Use a short and wide
trace to minimize the inductance and resistance of this connection.
Buck low side gate driver output of Port 0.
2
3
4
5
LG1_0
PGND_0
PVDD_0
LG2_0
Connect to the buck (input) side sync (low side) FET gate. Use a wide trace to minimize
inductance of this connection.
Ground of low side gate driver of Port 0. This is also connected to one input terminal
of zero current detection (ZCD) of buck low side gate driver.
Connect directly to Port 0’s board ground plane.
Supply of low side gate driver of Port 0.
Connect to VDDD. Use 1 µF and 0.1 µF bypass capacitors as close to the CCG7D IC as
possible.
Boost low side gate driver output of Port 0.
Connect to the boost (output) side control (low side) FET gate. Use a wide trace to
minimize inductance of this connection.
Output of the buck-boost converter of Port 0. This is also connected to one input
terminal of reverse current protection (RCP) of Boost high side gate driver.
Connect to the boost sync (high side) FET’s drain. Use a dedicated (Kelvin) trace for
this connection.
6
7
VOUT_0
SW2_0
Negative power rail of Port 0 boost high side gate driver. This is also connected to one
input terminal of RCP of boost high side gate driver
Connect to the switch node (inductor) on the boost (output) side. Use a short and wide
trace to minimize the inductance and resistance of this connection.
Boost high side gate driver output of Port 0.
–
8
9
HG2_0
Connect to the boost (output) side sync (high side) FET gate. Use a wide trace to
minimize inductance of this connection.
Boosted power supply of Port 0 boost high side gate driver. Bootstrap capacitor node.
Connect Schottky diode from VDDD to BST2_0. Also, connect a bootstrap capacitor
from this pin to SW2_0.
BST2_0
EA output pin of Port 0. Connect a compensation network to GND. Contact Infineon
for assistance in designing the compensation network.
10
11
12
COMP_0
CSPO_0
CSNO_0
Positive input of output current sensing amplifier of Port 0.
Connect to positive terminal of the output current sense resistor.
Negative input of output current sensing amplifier of Port 0.
Connect to negative terminal of the output current sense resistor.
Input of feedback voltage of error amplifier of Port 0.
Connect to the VBUS node between the output current sense resistor and the VBUS
provider NFET.
13
14
15
VBUS_IN_0
VBUS_C_0
CC1_0
Type-C connector VBUS voltage of Port 0.
Connect to the Type-C connector’s VBUS pin.
Type-C connector configuration channel 1 of Port 0.
Connect directly to the CC1 pin on the port’s Type-C connector. Also connect a 390-pF
capacitor to ground.
Type-C connector configuration channel 2 of Port 0.
Connect directly to the CC2 pin on the port’s Type-C connector. Also connect a 390-pF
capacitor to ground.
16
17
18
CC2_0
VBUS NFET gate driver output of Port 0.
Connect to the provider NFET’s gate.
VBUS_CTRL_0
GPIO / negative input terminal of Port 0’s VBAT – GND protection circuit.
Connect to the negative terminal of the VBAT – GND short protection current sense
resistor.
CSN_0_GPIO0
CSP_0_GPIO1
P0.0
P0.1
GPIO/ positive input terminal of Port 0’s VBAT – GND protection circuit.
Connect to the positive terminal of the VBAT – GND short protection current sense
resistor.
19
Datasheet
17
002-28172 Rev. *N
2023-01-31
INFINEON [ Infineon ]
