EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller
Dual-port
Power subsystem
2.1
VIN under-voltage lockout (UVLO)
CCG7D supports UVLO to allow the device to shut down when the input voltage is below the reliable level. It
guarantees predictable behavior when the device is up and running.
2.2
Using external VDDD supply
By default, external VDDD is not supported for CCG7D devices. However, usage of external VDDD supply can be
enabled using firmware. The pre-requisite for enabling external forcing of VDDD is to always maintain Vin higher
than VDDD and the external load on VDDD pin of CCG7D devices should never be higher than prescribed load
capability of internal VDDD LDO.
2.3
Power modes
Table 1 lists the power modes of the device accessible and observable by the user.
Table 1
Mode
Power modes
Description
Power is valid and XRES is not asserted. An internal reset source is asserted or sleep controller is
sequencing the system out of reset
Power is valid and CPU is executing instructions.
Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated
to save power.
RESET
ACTIVE
SLEEP
Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic, but only
low-frequency clock is available.
Power is valid and XRES is asserted. Core is powered down.
DEEP SLEEP
XRES
Datasheet
16
002-28172 Rev. *N
2023-01-31
INFINEON [ Infineon ]
