AN985B/BX
Registers and Descriptors Description
Function Present State Register
FPSR
Offset
108H
Reset Value
0000 0000H
Function Present State Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y
UR
UR
Field
Res
InEv
Bits
31:16
15
Type
ro
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Interrupt Event
This bit is used for interrupts. It reflects the current state of the Ethernet
source of the interrupt regardless of the mask value. It is set when the
Ethernet function hasa pending interrupt and cleared when the software
driver acknowledges all active interrups through the SCB Command
Word.
Res
GWUE
14:5
4
ro
ro
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is used for general wake-up. It reflects the current state of the
Ethernet source of CSTSCHG. It is a logical OR reseult of the gated three
most significant bits in the PMDR: Link Status change bit is gated by the
Link Status Change Wake Enable bit in the Configuration command. The
Magic Packet bit is gated by the Magic Packet Wake-up disable bit in the
Configuration command. The Interesting Packet bit is gated by the
programmable filter command.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Function Force Event Register
FFER
Offset
10CH
Reset Value
0000 0000H
Function Force Event Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8)
5HV
UR
5HV
UR
5HV
UR
)ꢀ
Z
Z
Field
Res
Bits
31:16
Type
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Data Sheet
80
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
