AN985B/BX
Registers and Descriptors Description
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
63
(ꢀ
/, 5H
1. V
(ꢁ
6/
)'
(7
5HV
UR
&0RGH
UR UR UR UR UZ UZ
UZ
Field
Bits
Type
Description
SPEED
31
ro
Network Speed Status
0B
1B
, 10M
, 100M
FD
30
29
ro
ro
Full/Half Duplex Status
0B
1B
, Half duplex
, Full duplex
LINK
Network Link Status
0B
1B
, Link off
, Link OK
Res
ET
28
27
ro
rw
Reserved
ET
0B
1B
, 9346
, 9366
E2SL
26
rw
E2prom_Soft_Load
Write 1 to reload e2prom
Res
CMode
25:3
2:0
ro
rw
Reserved
Chip Mode
These three bits are used to configure AN985B/BX’s chip mode:
111B , normal mode
110B , monitor mode
100B , HOME PNA mode
001B , phy only mode
101B , HP94000tester mode(vaux, vcc_detect will be internal forced to
1B, and muxed with poweron_reset input and ssram_rdy)
Function Event Register
FER
Offset
100H
Reset Value
0000 0000H
Function Event Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y
UOKꢊZꢁF
UZꢁF
Field
Res
Bits
31:16
Type
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Data Sheet
78
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
