AN985B/BX
Registers and Descriptors Description
Multicast Address Register 1
MAR1_CSR28
Multicast Address Register 1
Offset
B0H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
0$%ꢀ
0$%ꢁ
0$%ꢂ
0$%ꢃ
UZ
UZ
UZ
UZ
Field
Bits
Type
rw
rw
rw
rw
Description
MAB7
MAB6
MAB5
MAB4
31:24
23:16
15:8
7:0
Multicast Address Byte 7 (hash table 63:56)
Multicast Address Byte 6 (hash table 55:48)
Multicast Address Byte 5 (hash table 47:40)
Multicast Address Byte 4 (hash table 39:32)
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17 = 000)
Data Sheet
76
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
