AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
InEv
15
rlh/w1c Interrupt Event
This bit is used for as the interrupt bit. It is set when the Ethernet interrupt
source is set,regardless of the mask value. It is cleared when the OS
writes 1B to the field and the interrupt source has been serviced. Writing
0B to the field has no effect.
Res
GWUE
14:5
4
ro
rw1c
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is used for general wake-up. It is set when the Ethernet wake-up
source is set, regardless of the mask value. Writing 1B to the field clears
this bit and the PME status bit in the PMCSR. Writing 0B to the field has
no effect. Note that writing 1B to the PME status bit in the PMCSR has the
same effect.
Note:rw1c: Read only and Write one cleared.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Function Event Mask Register
FEMR
Offset
104H
Reset Value
0000 8000H
Function Event Mask Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q :8
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y 0
UZ UZ
UR
Field
Res
InEv
Bits
31:16
15
Type
ro
rw
Description
Bits[31:16] are reserved in the CARDBUS Specification
Interrupt Event
This bit is the interrupt mask. When the bit equals 0B, it masks the
Ethernet function CSTSCHG signal bit has no effect on the Function
Event Register. This bit is dependent on bit 4 of this register.
WUM
14
rw
Wake-Up Mask
When the bit equals 0B, it masks the Ethernet function INTA# line bus has
no effect on the Function Event Register. The interrupt mask
Res
GWUE
13:5
4
ro
ro
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is the general wake-up mask. When the bit equals 0B, it masks
Ethernet function wake-up events towards the CSTSCHG signal. It has
no effect on the Function Event register. The AN985B/BX can assert the
CSTSCHG signal in the following configuration of masked bits:wake-up
bit AND general wake-up bit, or PME Enable bit in the PMCSR register
only.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Data Sheet
79
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
