AN985B/BX
Registers and Descriptors Description
Unicast Address Register 0
UAR0_CSR_29
Unicast Address Register 0
Offset
B4H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
8$%ꢀ
8$%ꢁ
8$%ꢂ
8$%ꢃ
UZ
UZ
UZ
UZ
Field
UAB3
UAB2
UAB1
UAB0
Bits
Type
rw
rw
rw
rw
Description
31:24
23:16
15:8
7:0
Unicast Address Byte 3 (hash table 31:24)
Unicast Address Byte 2 (hash table 23:16)
Unicast Address Byte 1 (hash table 15:8)
Unicast Address Byte 0 (hash table 7:0)
Unicast Address Register 1
UAR1_CSR_30
Unicast Address Register 1
Offset
B8H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
8$%ꢀ
8$%ꢁ
8$%ꢂ
8$%ꢃ
UZ
UZ
UZ
UZ
Field
UAB7
UAB6
UAB5
UAB4
Bits
Type
rw
rw
rw
rw
Description
31:24
23:16
15:8
7:0
Unicast Address Byte 7 (hash table 63:56)
Unicast Address Byte 6 (hash table 55:48)
Unicast Address Byte 5 (hash table 47:40)
Unicast Address Byte 4 (hash table 39:32)
Unicast64 Algorithm
The algorithm is the same with multicast64.
Operation Mode Register
OMR
Offset
FCH
Reset Value
0000 0007H
Operation Mode Register
Data Sheet
77
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
