AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
SPEED
13
rw
Speed Selection
0B
1B
, 10 Mbit/s
, 100 Mbit/s
ANE
PD
IS
12
11
10
rw
rw
rw
Autonegotiation Enable
0B
1B
, disable autoneg
, enable autoneg
Power Down
0B
1B
, normal operation
, Power Down
Isolate
0B
1B
, normal operation
, isolate PHY from MII
RAN
DM
9
8
rwsc
rw
Restart Autonegotiation
1B , Restart Autoneg
Duplex Mode
0B
1B
, half duplex
, full duplex
CT
7
ro
ro
Collision Test
Not implemented
Res
6:0
Reserved
SC: Self Clearing
Reset: Reset this port only. This will cause the following:
1. Restart the autonegotiation process.
2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These
registers are not reset by this bit to allow test configurations to be written and then not affected by resetting the
port.
Note:No reset is performed to analogue sections of the port. There is also no physical reset to any internal clock
synthesizers or the local clock recovery oscillator which will continue to run throughout the reset period.
However since the port is restarted and autoneg re-run the process of locking the frequency of the local
oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization
process.
Loopback: Loop back of transmit data to receive via a path as close to the wire as possible. When set inhibits
actual transmission on the wire.
Speed selection: Forces speed of Phy only when autonegotiation is disabled. The default state of this bit will be
determined by a power-up configuration pin in this case. Otherwise it defaults to 1.
Auto-neg enable Defaults to pin programmed value. When cleared allows forcing of speed and duplex settings.
When set (after being cleared) causes re-start of autoneg process. Pin programming at power-up allows it to come
up disabled and for software to write the desired capability before allowing the first negotiation to commence.
Restart Negotiation: only has effect when autonegotiating. Restarts state machine.
Power down: Has no effect in this device. Test mode power down modes may be implemented in other specific
modules.
Isolate: Puts RMII receive signals into high impedance state and ignores transmit signals.
Duplex mode: When bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex
(bit = 0).
Data Sheet
84
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
