AN985B/BX
Registers and Descriptors Description
Transmit Burst Count/Time-out
TXBR_CSR23
Transmit Burst Count/Time-out
Offset
9CH
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
7%&17
5HV
772
UZ
UZ
Field
Res
Bits
31:21
Type
ro
Description
Reserved
TBCNT
20:16
rw
Transmit Burst Count
After this number of consecutive successful transmit, transmit completed
interrupt will be generated. Continuously do this function if no reset.
TTO
11:0
rw
Transmit Time-Out = (deferred time + back-off time)
When the TDIE (bit28 of ACSR7) is set, the timer is decreased in unit of
2.56 μ s (100M) or 25.6 μ s (10M). If the timer expires before another
packet transmit begin, then the TDIE interrupt will be generated.
Flash ROM (also the boot ROM) Port
FROM_CSR24
Flash ROM (also the boot ROM) Port
Offset
A0H
Reset Value
8000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%2
1
5(:(
1 1
5HV
UR
$''5
'$7$
UZ
UZ UZ
UZ
UZ
Field
BON
Bits
31
Type
rw
Description
Bra16_on
This bit is no effective when 3_LED scheme applied.
Driver needs to program this bit when 4_LED applied especially when
boot rom read.
0B
1B
, bra[16]=fd/col LED path
, no effect to bar[16]
Res
REN
30:28
27
ro
rw
Reserved
Read Enable
Clear if read data is ready in DATA, bit7-0 of FROM.
WEN
26
rw
Write Enable
Cleared if write completed.
Data Sheet
73
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
