AN985B/BX
Registers and Descriptors Description
CARDBUS Bus Performance Counter
CARDBUSC_CSR19
CARDBUS Bus Performance Counter
Offset
8CH
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
&/.&17
5HV
UR
':&17
URꢊ
URꢊ
Field
CLKCNT
Bits
31:16
Type
ro*
Description
Clock Count
The number of CARDBUS clock from read request asserted to access
completed. This CARDBUS clock number is accumulated all the read
command cycles from last CSR19 read to current CSR19 read.
Note:ro*: Read only and cleared by reading
Reserved
Double Word Count
Res
DWCNT
15:8
7:0
ro
ro*
The number of double word accessed by the last bus master. This double
word number is accumulated all the bus master data transactions from
last CSR19 read to current CSR19 read.
Note:ro*: Read only and cleared by reading
ro = Read only and cleared by reading
Power Management Command and Status
(The same register value mapping to CR49-PMR1)
PMCSR_CSR20
Power Management Command and Status
Offset
90H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
30 '6&$
30
(ꢀ
5HV
UR
'6(/
5HV
UR
3:56
(6
/
UR UR
UR
UR
UR
Field
Res
Bits
31:16
Type
ro
Description
Reserved
Data Sheet
70
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
