AN985B/BX
Registers and Descriptors Description
Assistant CSR7 (Interrupt Enable Register 2)
ACSR7_CSR17
Assistant CSR7 (Interrupt Enable Register 2)
Offset
84H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
7( 5( /& 7' 5H 3)
,( ,( ,( ,( V 5ꢀ
$1$$
,ꢀ ,(
5HV
UR
&65ꢁ
UZ UZ UZ UZ UR UZ
UZ UZ
UR
Field
TEIE
REIE
LCIE
TDIE
Res
Bits
31
30
29
28
Type
Description
rw
rw
rw
rw
ro
Transmit Early Interrupt Enable
Receive Early Interrupt Enable
Link Status Change Interrupt Enable
Transmit Deferred Interrupt Enable
Reserved
27
PFRIE
Res
ANISE
26
25:17
16
rw
ro
rw
PAUSE Frame Received Interrupt Enable
Reserved
Added Normal Interrupt Summary Enable
1B
, adds the interrupts of bit 30 and 31 of ACSR7 to the normal
interrupt summary (bit 16 of CSR5)
AAIE
15
rw
ro
Added Abnormal Interrupt Summary Enable
1B
, adds the interrupt of bit 26, 28 and 29 of ACSR7 to the abnormal
interrupt summary
CSR7
14:0
This bits are the same as CSR7
You can access those status bits through either CSR7 or CSR16
Command Register
Bit 31 to Bit 16
Automatically recall from EEPROM
CR_CSR18
Command Register
Offset
88H
Reset Value
A04C 0004H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
'ꢀ
&6
30303&
ꢂB
ꢀ/
&5
'
$3/:
0 6
3/ 'ꢀ5:3$ 57
6 $ 3 8ꢁ (
6, $7
$8;&/
36
5)6
30
5HV
UR
'57
(ꢁ (ꢁ
,
17 85
UZ
UR
UZ UZ UZ UZ UZ UZ UZ UR UZ UZ
UZ UZ UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
D3CS
31
rw
D3cold Support, Mapped to CR48<31>
Data Sheet
67
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
