AN985B/BX
Registers and Descriptors Description
Assistant CSR5 (Status Register 2)
ACSR5_CSR16
Assistant CSR5 (Status Register 2)
Offset
80H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
7( 5( /& 7' 5H 3)
,6 ,6 6 ,6 V
$1$$
,ꢀ ,ꢀ
5HV
UR
&65ꢁ
5
URꢊOKURꢊOKURꢊOKURꢊOKURURꢊOK
URꢊOKURꢊOK
UR
Field
TEIS
Bits
31
Type
ro/lh
Description
Transmit Early Interrupt Status
Transmit early interrupt status is set to 1 when Transmit early interrupt
function is enabled (set bit 31 of CSR17 = 1) and the transmitted packet
is moved completed from descriptors to TX-FIFO buffer. This bit is
cleared by written with 1.
Note:LH = High Latching and cleared by writing 1
REIS
30
ro/lh
Receive Early Interrupt Status
Receive early interrupt status is set to 1 when Receive early interrupt
function is enabled (set bit 30 of CSR17 = 1) and the received packet is
fill up its first receive descriptor. This bit is cleared by written with 1.
Note:LH = High Latching and cleared by writing 1
Status of Link Status Change
Note:LH = High Latching and cleared by writing 1
Transmit Deferred Interrupt Status
Note:LH = High Latching and cleared by writing 1
Reserved
LCS
29
28
ro/lh
ro/lh
TDIS
Res
PFR
27
26
ro
ro/lh
PAUSE Frame Received Interrupt Status
Note:LH = High Latching and cleared by writing 1
1B
, indicates a PAUSE frame received when the PAUSE function is
enabled
Res
ANISS
25:17
16
ro
ro/lh
Reserved
Added Normal Interrupt Status Summary
Note:LH = High Latching and cleared by writing 1
1B
, any of the added normal interrupts happened
AAISS
CSR5
15
ro/lh
ro
Added Abnormal Interrupt Status Summary
Note:LH = High Latching and cleared by writing 1
1B
, any of added abnormal interrupt happened
14:0
This bits are the same as CSR5
You can access those status bits through either CSR5 or CSR16
Data Sheet
66
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
